1. Field of the Invention
The present invention relates to a test method, and in particular to a method for detecting whether the alignment of bit line contacts and active areas in DRAM devices is normal, as well as a test device thereof.
2. Description of the Related Art
FIG. 1 is a layout of conventional deep trench capacitors in a memory device. Deep trench capacitors 10 are disposed under the passing word lines. Transistors 14 are electrically coupled to the storage nodes 16 of the capacitors 10 through the diffusion regions 18. The diffusion regions 20 are connected to plugs 22 coupled to bit lines (not shown). The transistors 14 are driven by word lines 12, the channels under the word lines 12 are conductive when appropriate voltages are applied to the word lines 12. Consequently, the current produced between the diffusion regions 18 and 20 may flow into or out of the storage nodes 16.
After the deep trench capacitors 10 are completely formed in the substrate, trench isolations are formed in the substrate and deep trench capacitors 10 to define active areas. The word lines 12 are then formed on the substrate, the diffusion regions 18 and 20 are formed in the active areas by word lines 12 during the implant process, and the diffusion regions 18 and 20 are located on two sides of the word lines 12. Finally, the plugs 22 are formed on the diffusion regions 20. The adjacent memory cells may have a current leakage and cell failure which reduce the process yield if the masks of active areas and the bit line contacts did not align accurately.
Therefore, the process yield and reliability of the memory cells can be improved if alignment inaccuracy between the masks of active areas and the bit line contacts can be controlled within an acceptable range.